Many communication networks that provide high bit-rate transport over a shared medium are characterized by non-continuous or burst mode data transmission. An example for such network is a passive optical network (PON) 100 schematically shown in FIG. 1. A typical PON 100 includes a plurality of optical network units ONUs 120-1 through 120-M coupled to an OLT 130 via a passive optical splitter 140. Since all ONUs function in like manner, they will be collectively referred to by the reference numeral 120 in the following description unless reference is made to a specific ONU. Traffic data transmission may be achieved using GEM fragments or ATM cells over two optical wavelengths, one for the downstream direction and another for the upstream direction. Thus, downstream transmission from the OLT 130 is broadcast to all the ONUs 120. Each ONU 120 filters its respective data according to, for example, pre-assigned labels.
The OLT 130 continuously transmits downstream data to the ONUs 120 and receives upstream burst data sent to OLT 130 from ONUs 120. The OLT 130 broadcasts data to the ONUs 120 along a common channel so that all the ONUs 120 receive the same data. An ONU 120 transmits data to the OLT 130 during different time slots allocated by the OLT 130. That is, the OLT 130 is aware of the exact arrival time of data and the identity of a transmitting ONU 120.
A receiver in the OLT 130 uses a burst mode clock and data recovery (BCDR) circuit to generate a clock corresponding to the incoming data, thereby correctly retiming the incoming data. In the case of burst data transmission, a preamble is transmitted before the data to obtain the clock information before sampling the data.
Conventional clock and data recovery (CDR) and BCDR circuits are typically based on a phase locked loop (PLL) or over-sampling techniques. Examples of PLL based CDR and BCDR circuits may be found in U.S. Pat. Nos. 5,757,872, 5,237,290 and 6,259,326 as well as in US patent publications US2005281366 (Shachar et al.), US2006115035 (Yu et al.) and US2006031701 (Nam et al.) all of which are incorporated herein by reference for their useful background information.
In over-sampling based CDR and BCDR techniques, in general, data is obtained by sampling data over a multiphase clock. FIG. 2 shows a schematic block diagram of a typical over-sampling based BCDR circuit 200. The BCDR circuit 200 includes a reference oscillator 210 and a phase interpolator 220 that are used together to provide a number N of clock signals at the oscillating frequency generated by the oscillator 210. Each such clock signal is shifted in phase by a factor 1/N of the clock cycle with respect to the preceding signal. The clock signals are input into an over-sampler 230 utilized to retime the data and clock. The over-sampler 230 receives an input data signal and, using the clock signals, generates a digital representation of at least one complete period of the input data signal. A phase estimation circuit (PEC) 240 receives this digital representation and uses that representation to generate an estimate of the phase of the input data signal, as received. This estimate is input into the phase interpolator 220 to generate a correct sampling clock signal (e.g., the clock signal having a sampling edge closest to the middle of the bit-interval of input data signal) for future sampling of the input data signal. The PEC 240 also produces frequency information to align the recovered clock with the transmitted clock. Examples of over-sampling based CDR circuits may be found in U.S. Ser. No. 10/460,572 and in U.S. Pat. Nos. 6,122,335, 6,259,326 and 6,269,137, which are incorporated herein by reference for their useful background information. The over-sampling based CDR circuits are capable of both fast locking to a rapidly changed phase of the transmission clock and stable tracking of a slowly changing phase.